Generation of new power processing structures exploiting genetic programming

This paper describes the use of genetic algorithms to generate power processing circuits. In order to speed up the algorithm, the fitness of the circuits is evaluated using an explicit integration method based on the 4th order Adams–Bashforth formula. Different combinations of genetic primitives for the crossover and mutation processes have been tested. The algorithm is demonstrated by generating new structures of voltage multipliers, which specifically focus on energy harvesting systems. These systems require low input voltages, usually under the diode threshold value. The Adams–Bashforth method allows to achieve a simulation time that is about five times faster than that of SPICE-based simulations.This work was partially funded by Spanish government project TEC2015-66878-C3-2-R (MINECO/FEDER, UE)

Massively-parallel bit-serial neural networks for fast epilepsy diagnosis: a feasibility study

There are about 1% of the world population suffering from the hidden disability known as epilepsy and major developing countries are not fully equipped to counter this problem. In order to reduce the inconvenience and danger of epilepsy, different methods have been researched by using a artificial neural network (ANN) classification to distinguish epileptic waveforms from normal brain waveforms. This paper outlines the aim of achieving massive ANN parallelization through a dedicated hardware using bit-serial processing. The design of this bit-serial Neural Processing Element (NPE) is presented which implements the functionality of a complete neuron using variable accuracy. The proposed design has been tested taking into consideration non-idealities of a hardware ANN. The NPE consists of a bit-serial multiplier which uses only 16 logic elements on an Altera Cyclone IV FPGA and a bit-serial ALU as well as a look-up table. Arrays of NPEs can be driven by a single controller which executes the neural processing algorithm. In conclusion, the proposed compact NPE design allows the construction of complex hardware ANNs that can be implemented in a portable equipment that suits the needs of a single epileptic patient in his or her daily activities to predict the occurrences of impending tonic conic seizures

Simulation acceleration of image filtering on CMOS vision chips using many-core processors

This paper describes an efficient numerical solution to speed up transient simulations of analog circuits on a many-core computer. The technique is based on an explicit integration method, parallelised on a multiprocessor architecture. Although the integration step is smaller than the required one by traditional simulation methods based on Newton–Raphson iterations, explicit methods do not require to compute complex calculations such us matrix factorizations, which lead to long CPU simulation times. The proposed technique has been implemented on a NVIDIA GPU and has been demonstrated simulating Gaussian filtering operations performed by a CMOS vision chip. These type of devices, which are used to perform computation on the edge, include built-in image processing functions, turning them into very complex and time consuming circuits during their design. The proposed method is faster that Ngspice for different image sizes, and for 128 x 128 pixels image size it achieves a speed up of two orders of magnitude.This work has been partially funded by Spanish government through project RTI2018-097088-B-C33 and by EPSRC (the UK Engineering and Physical Sciences Research Council) under grant EP/N0317681/1. The research stays at University of Southampton (UK) have been supported by Ministerio de Educación, Cultura y Deporte within the “Programa Estatal de Promoción del Talento y su Empleabilidad en I+D+i, Subprograma Estatal de Movilidad, del Plan Estatal de I+D+I” under grant PRX18/00565 and by Universidad Politécnica de Cartagena - Campus de Excelencia Internacional Mare Nostru

Stability and efficiency of explicit integration in interconnect analysis on GPUs

This paper presents a technique to parallelise a numeric integration solver on general purpose GPU. The technique is based on the combination of space state modeling with an explicit integration method based on the Adams-Bashforth second order formula. The paper studies the stability of variable step explicit method and proposes a technique to guarantee integration stability using this technique. Although explicit methods require smaller integration steps compared to the traditional implicit techniques, they avoid the complex calculations on large which are used to solve the last ones. The technique is demonstrated simulating an RC model of an VLSI interconnect. Results achieved by the proposed variable step explicit method is compared to those achieved by a traditional implicit integration based simulator like Ngspice. The results show that the parallelised explicit solution is one order of magnitude faster than the implicit one for increasingly complex circuits.This work has been partially funded by Spanish government through project RTI2018-097088-B-C33 (MINECO/FEDER, UE) and by EPSRC (the UK Engineering and Physical Sciences Research Council) under grant EP/N0317681/1. The research stay at The University of Southampton has been supported by Fundacion Séneca-Agencia de Ciencia y Tecnología de la Región de Murcia, Programa Regional de Movilidad, Colaboración e Intercambio de Conocimiento Jimenez de la Espada under grant 21187/EE/1

High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors

This work describes a high-speed simulation technique of analog circuits which is based on the use of statespace equations and an explicit integration method parallelised on a multiprocessor architecture. The integration step of such method is smaller than the one required by an implicit simulation technique based on Newton–Raphson iterations. However, given that explicit methods do not require the computation of time-consuming matrix factorizations, the overall simulation time is reduced. The technique described in this work has been implemented on a NVIDIA general purpose GPU and has been tested simulating the Gaussian filtering operation performed by a smart CMOS image sensor. Such devices are used to perform computation on the edge and include built-in image processing functions. Among those, the Gaussian filtering is one of the most common functions, since it is a basic task for early vision processing. These smart sensors are increasingly complex and hence the time required to simulate them during their design cycle is also larger and larger. From a certain imager size, the proposed simulation method yields simulation times two order of magnitude faster that an implicit method based tool such us SPICEThis work has been partially funded by Spanish government through project RTI2018-097088-B-C33 (MINECO/FEDER, UE) and by EPSRC (the UK Engineering and Physical Sciences Research Council) under grant EP/N0317681/1. The research stay at University of Southampton (UK) has been supported by Ministerio de Educación, Cultura y Deporte within the “Programa Estatal de Promoción del Talento y su Empleabilidad en I+D+i, Subprograma Estatal de Movilidad, del Plan Estatal de I+D+I” under grant PRX18/00565

VHDL-AMS modeling of self-organizing neural systems

This paper presents VHDL-AMS models and simulation results for a complex, self-organizing neural system based on the adaptive resonance theory. Such neural systems exhibit both discrete and continuous dynamic behavior and consist of a large number of analog equations, a digital controller with analog and digital feedback paths resulting in the complexity that would prohibit analysis with conventional mixed-signal simulation tools

Energy Efficient Sensor Nodes Powered by Kinetic Energy Harvesters – Design for Optimum Performance

In an energy harvester powered wireless sensor node system, as the energy harvester is the only energy source, it is crucial to configure the microcontroller and the sensor node so that the harvested energy is used efficiently. This paper outlines modelling, performance optimisation and design exploration of the complete, complex system which includes the analogue mechanical model of a tunable kinetic microgenerator, its magnetic coupling with the electrical blocks, electrical power storage and processing parts, the digital control of the microgenerator tuning system, as well as the power consumption models of sensor node. Therefore not only the energy harvester design parameters but also the sensor node operation parameters can be optimised in order to achieve the best system performance. The power consumption models of the microcontroller and the sensor node are built based on their operation scenarios so that the parameters of the digital algorithms can be optimised to achieve the best energy efficiency. In the proposed approach, two Hardware Description Languages, VHDL-AMS and SystemC-A is used to model the system's analogue components as well as the digital control algorithms which are implemented in the microcontroller and the sensor node. Simulation and performance optimisation results are verified experimentally. In the development of the fast design exploration tool based on the response surface technique, the response surface model (RSM) is constructed by carrying out a series of simulations. The RSM is then optimised using MATLAB's optimisation toolbox and the optimisation results are presented

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%

Synchronization of Analogue and Digital Solvers in Mixed-Signal Simulation on a SystemC Platform

This contribution proposes a synchronization technique for solvers able to handle analogue extensions to SystemC, for modelling of general, mixed-mode systems with digital and non-linear analogue behaviour. In order to comply with the SystemC simulation cycle semantics, we link the analogue kernel to the SystemC environment as a user module and synchronize it with the SystemC kernel via a lockstep synchronization algorithm. Operation of the extended, mixed-signal SystemC simulation platform is demonstrated using the practical example of a boost power converter, in which analogue behaviour interacts with a digital control loop. We hope that the result presented here might aid the recent efforts to standardize analogue extensions for SystemC

Energy Efficient Multi-Core Processing

This paper evaluates the present state of the art of energy-efficient embedded processor design techniques and demonstrates, how small, variable-architecture embedded processors may exploit a run-time minimal architectural synthesis technique to achieve greater energy and area efficiency whilst maintaining performance. The picoMIPS architecture is presented, inspired by the MIPS, as an example of a minimal and energy efficient processor. The picoMIPS is a variablearchitecture RISC microprocessor with an application-specific minimised instruction set. Each implementation will contain only the necessary datapath elements in order to maximise area efficiency. Due to the relationship between logic gate count and power consumption, energy efficiency is also maximised in the processor therefore the system is designed to perform a specific task in the most efficient processor-based form. The principles of the picoMIPS processor are illustrated with an example of the discrete cosine transform (DCT) and inverse DCT (IDCT) algorithms implemented in a multi-core context to demonstrate the concept of minimal architecture synthesis and how it can be used to produce an application specific, energy efficient processor